1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device (EEPROM) using electrically programmable memory cells each having a charge accumulation layer such as a floating gate and a control gate and, more particularly, to an EEPROM having a memory cell array having a NAND cell arrangement.
2. Description of the Related Art
As one of conventional EEPROMs, a NAND EEPROM which can be integrated at a high density is known. In the NAND EEPROM, a plurality of memory cells are coupled in series with each other such that the source and drain of adjacent memory cells are commonly used for the memory cells, and the coupled memory cells are defined as one unit coupled to a bit line. This one unit is defined as a NAND cell. Each memory cell generally has a MOS structure obtained by stacking a floating gate and a control gate. The drain side of each NAND cell is coupled to the bit line through a selection gate, and the source side is coupled to a source line (reference potential wiring line) through a selection gate. The control gates of the memory cells are sequentially arranged in a row direction to become word lines.
In recent years, as an improved NAND EEPROM, an EEPROM in which the number of contacts between bit lines and drains is decreased by improving a selection gate is proposed (Jpn. Pat. Appln. KOKAI Publication No. 2-74069). This EEPROM is constituted as follows. A bit line is coupled to a drain diffusion layer through a drain contact hole, and two first selection transistor arrays are arranged to be coupled to the drain diffusion layer. The first selection transistors are constituted by properly connecting an enhancement transistor in series with a depletion transistor, a source line is arranged perpendicular to the bit line, and one second selection transistor array is arranged to be coupled to the source line. A plurality of cell transistors each having a floating gate and a control gate are coupled in series with the two first selection transistor arrays and the second selection transistor array.
With the above arrangement, only one bit line and one drain contact are required for the two adjacent NAND cell arrays, and the number of bit lines and the number of drain contact holes can be decreased to increase a degree of integration in the word line direction.
In the above device, data is erroneously written in a data write operation. This problem will be described below with reference to FIG. 1.
In an EEPROM shown in FIG. 1, in a data write operation, the potential of a bit line BL is set to be 0 V, a gate potential SG.sub.1 of first selection transistors is set at "H", SG.sub.2 =0 V, a gate potential SG.sub.3 of second selection transistors is set to be 0 V, a control gate potential CG.sub.1 on a drain contact side from a memory cell in which data is to be written is set to be 20 V, and a control gate potential CG.sub.2 of other memory cells is set to be 0 V.
In this case, the left transistor of the first selection transistors is turned on, the right transistor is turned off, and both the second selection transistors are turned off. Since the drain and gate of the memory cell in which data is to be written are set to be 0 V and 20 V, respectively, electrons are extracted to the drain from the floating gate of the memory cell to change the threshold voltage of the memory cell. That is, a write operation is performed to the memory cell. Since a source/drain diffusion layer is set in a floating state in the right NAND cell, even when the control gate of the memory cell on the drain contact side from the memory cell in which data is to be written is set to be 20 V, no electrons are injected into the memory cell. Therefore, the threshold voltage of the memory cell does not change.
However, in practical use, when a substrate temperature is at a temperature, e.g., 20 to 80.degree., pairs of electrons and holes are easily generated in an Si substrate, in the memory cell to which the control gate is set to the potential 20 V, electrons generated in the substrate due to the above pairs are injected into the floating gate, thereby changing the threshold voltage. That is, an erroneous write operation is performed in the memory cell. This change in threshold voltage is caused by, e.g., crystal defects. The change may occur even in at room temperature. Therefore, although a process free from crystal defects is required, a process margin must be decreased to realize this process.
As described above, in a conventional EEPROM in which one bit line and one drain contact are used in two NAND cell arrays, the source and drain of each non-selected memory cell are set in a floating state. For this reason, electrons generated by a substrate are injected into the floating gate to cause an erroneous write operation.